Cypress CY7C1316CV18 User Manual

CY7C1316CV18, CY7C1916CV18

CY7C1318CV18, CY7C1320CV18

18-Mbit DDR-II SRAM 2-Word

Burst Architecture

Features

Functional Description

■ 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36)

■ 267 MHz clock for high bandwidth

The CY7C1316CV18, CY7C1916CV18, CY7C1318CV18, and

CY7C1320CV18 are 1.8V Synchronous Pipelined SRAMs

equipped with DDR-II architecture. The DDR-II consists of an

SRAM core with advanced synchronous peripheral circuitry and

a one-bit burst counter. Addresses for read and write are latched

on alternate rising edges of the input (K) clock. Write data is

registered on the rising edges of both K and K. Read data is

driven on the rising edges of C and C if provided, or on the rising

edge of K and K if C/C are not provided. Each address location

is associated with two 8-bit words in the case of CY7C1316CV18

and two 9-bit words in the case of CY7C1916CV18 that burst

sequentially into or out of the device. The burst counter always

starts with a ‘0’ internally in the case of CY7C1316CV18 and

CY7C1916CV18. For CY7C1318CV18 and CY7C1320CV18,

the burst counter takes in the least significant bit of the external

address and bursts two 18-bit words (in the case of

CY7C1318CV18) of two 36-bit words (in the case of

CY7C1320CV18) sequentially into or out of the device.

■ 2-word burst for reducing address bus frequency

■ Double Data Rate (DDR) interfaces

(data transferred at 534 MHz) at 267 MHz

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Two input clocks for output data (C and C) to minimize clock

skew and flight time mismatches

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Synchronous internally self-timed writes

■ DDR-II operates with 1.5 cycle read latency when the DLL is

enabled

Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs (Q, sharing the same

physical pins as the data inputs, D) are tightly matched to the two

output echo clocks CQ/CQ, eliminating the need to capture data

separately from each individual DDR SRAM in the system

design. Output data clocks (C/C) enable maximum system

clocking and data synchronization flexibility.

■ Operates similar to a DDR-I device with 1 cycle read latency in

DLL off mode

■ 1.8V core power supply with HSTL inputs and outputs

■ Variable drive HSTL output buffers

■ Expanded HSTL output voltage (1.4V–V

)

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

■ Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

Configurations

CY7C1316CV18 – 2M x 8

CY7C1916CV18 – 2M x 9

CY7C1318CV18 – 1M x 18

CY7C1320CV18 – 512K x 36

Selection Guide

Description

267 MHz

267

250 MHz

250

200 MHz

200

167 MHz

167

Unit

MHz

Maximum Operating Frequency

Maximum Operating Current

775

705

575

490

780

710

580

490

x18

x36

805

730

600

510

855

775

635

540

Cypress Semiconductor Corporation

Document Number: 001-07160 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 18, 2008

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CY7C1316CV18, CY7C1916CV18

CY7C1318CV18, CY7C1320CV18

Logic Block Diagram (CY7C1318CV18)

Burst

Logic

Write

Reg

Write

Reg

20 19

(19:0)

Address

(19:1)

Output

R/W

CLK

Logic

Gen.

Control

DOFF

Read Data Reg.

REF

Reg.

Control

Logic

R/W

BWS

[1:0]

[17:0]

Logic Block Diagram (CY7C1320CV18)

Burst

Logic

Write

Reg

Write

Reg

19 18

(18:0)

Address

(18:1)

Output

Logic

Control

CLK

R/W

Gen.

DOFF

Read Data Reg.

REF

Reg.

Control

Logic

R/W

BWS

[3:0]

[35:0]

Document Number: 001-07160 Rev. *E

Page 3 of 29

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CY7C1318CV18, CY7C1320CV18

Pin Configuration

[1]

The pin configuration for CY7C1316CV18, CY7C1916CV18, CY7C1318CV18, and CY7C1320CV18 follow.

165-Ball FBGA (13 x 15 x 1.4 mm) Pinout

CY7C1316CV18 (2M x 8)

DOFF

TDO

NC/72M

R/W

NC/36M

DQ3

DQ2

NWS

NC/144M

DQ4

DQ5

NC/288M

NWS

DDQ

REF

DDQ

DQ1

DQ0

TDI

DQ7

DQ6

TCK

TMS

CY7C1916CV18 (2M x 9)

DOFF

TDO

NC/72M

NC/36M

DQ3

R/W

NC/144M

DQ4

DQ5

NC/288M

BWS

DQ2

DDQ

REF

DDQ

DQ1

DQ7

DQ6

DQ0

DQ8

TDI

TCK

TMS

Note

1. NC/36M, NC/72M, NC/144M, and NC/288M are not connected to the die and can be tied to any voltage level.

Document Number: 001-07160 Rev. *E

Page 4 of 29

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CY7C1316CV18, CY7C1916CV18

CY7C1318CV18, CY7C1320CV18

Pin Configuration (continued)

[1]

The pin configuration for CY7C1316CV18, CY7C1916CV18, CY7C1318CV18, and CY7C1320CV18 follow.

165-Ball FBGA (13 x 15 x 1.4 mm) Pinout

CY7C1318CV18 (1M x 18)

DOFF

TDO

NC/72M

DQ9

R/W

NC/36M

BWS

NC/144M

NC/288M

BWS

DQ8

DQ7

DQ10

DQ11

DQ6

DQ5

DDQ

DQ12

DQ13

REF

DDQ

DQ14

DQ4

DQ3

DQ2

DQ15

DQ1

DQ16

DQ17

DQ0

TDI

TCK

TMS

CY7C1320CV18 (512K x 36)

DOFF

TDO

BWS

NC/72M

NC/144M NC/36M

R/W

DQ27

DQ18

DQ28

DQ19

DQ20

DQ21

DQ22

DQ8

DQ7

DQ16

DQ6

DQ5

DQ14

DQ17

DQ29

DQ15

DDQ

DQ30

DQ31

REF

DDQ

DQ32

DQ23

DQ24

DQ34

DQ25

DQ26

DQ13

DQ12

DQ4

DQ3

DQ2

DQ1

DQ10

DQ0

TDI

DQ33

DQ11

DQ35

DQ9

TMS

TCK

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CY7C1318CV18, CY7C1320CV18

Pin Definitions

Pin Name

Pin Description

Input Output- Data Input Output Signals. Inputs are sampled on the rising edge of K and K clocks during valid write

Synchronous operations. These pins drive out the requested data during a read operation. Valid data is driven out on

the rising edge of both the C and C clocks during read operations or K and K when in single clock mode.

[x:0]

When read access is deselected, Q

are automatically tri-stated.

[x:0]

CY7C1316CV18 − DQ

[7:0]

CY7C1916CV18 − DQ

[8:0]

CY7C1318CV18 − DQ

CY7C1320CV18 − DQ

[17:0]

[35:0]

NWS ,

Input-

Synchronous Load. This input is brought LOW when a bus cycle sequence is defined. This definition

Synchronous includes address and read/write direction. All transactions operate on a burst of 2 data.

Input-

Nibble Write Select 0, 1 − Active LOW (CY7C1316CV18 only). Sampled on the rising edge of the K

NWS

Synchronous and K clocks during write operations. Used to select which nibble is written into the device during the

current portion of the write operations. Nibbles not written remain unaltered.

NWS controls D

and NWS controls D

[3:0]

[7:4]

All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select

ignores the corresponding nibble of data and it is not written into the device.

BWS ,

Input-

Byte Write Select 0, 1, 2, and 3 − Active LOW. Sampled on the rising edge of the K and K clocks during

BWS ,

Synchronous write operations. Used to select which byte is written into the device during the current portion of the Write

operations. Bytes not written remain unaltered.

BWS ,

BWS

CY7C1916CV18 − BWS controls D

[8:0]

CY7C1318CV18 − BWS controls D

and BWS controls D

[17:9].

CY7C1320CV18 − BWS controls D

[35:27]

, BWS controls D

and BWS controls

[8:0]

[17:9]

[26:18]

All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select

ignores the corresponding byte of data and it is not written into the device.

A, A0

Input-

Address Inputs. These address inputs are multiplexed for both read and write operations. Internally, the

Synchronous device is organized as 2M x 8 (2 arrays each of 1M x 8) for CY7C1316CV18 and 2M x 9 (2 arrays each

of 1M x 9) for CY7C1916CV18, 1M x 18 (2 arrays each of 512K x 18) for CY7C1318CV18, and 512K x

36 (2 arrays each of 256K x 36) for CY7C1320CV18.

CY7C1316CV18 – Because the least significant bit of the address internally is a ‘0’, only 20 external

address inputs are needed to access the entire memory array.

CY7C1916CV18 – Because the least significant bit of the address internally is a ‘0’, only 20 external

address inputs are needed to access the entire memory array.

CY7C1318CV18 – A0 is the input to the burst counter. These are incremented internally in a linear fashion.

20 address inputs are needed to access the entire memory array.

CY7C1320CV18 – A0 is the input to the burst counter. These are incremented internally in a linear fashion.

19 address inputs are needed to access the entire memory array. All the address inputs are ignored when

the appropriate port is deselected.

R/W

Input-

Synchronous Read/Write Input. When LD is LOW, this input designates the access type (read when

Synchronous R/W is HIGH, write when R/W is LOW) for the loaded address. R/W must meet the setup and hold times

around the edge of K.

Input Clock Positive Input Clock for Output Data. C is used in conjunction with C to clock out the read data from

the device. C and C can be used together to deskew the flight times of various devices on the board back

to the controller. See Application Example on page 9 for more information.

Input Clock Negative Input Clock for Output Data. C is used in conjunction with C to clock out the read data from

the device. C and C can be used together to deskew the flight times of various devices on the board back

to the controller. See Application Example on page 9 for more information.

Input Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device

and to drive out data through Q

edge of K.

when in single clock mode. All accesses are initiated on the rising

[x:0]

Input Clock Negative Input Clock Input. K is used to capture synchronous data being presented to the device and

to drive out data through Q when in single clock mode.

[x:0]

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CY7C1316CV18, CY7C1916CV18

CY7C1318CV18, CY7C1320CV18

Pin Definitions (continued)

Pin Name

Pin Description

Output Clock CQ Referenced with Respect to C. This is a free running clock and is synchronized to the input clock

for output data (C) of the DDR-II. In single clock mode, CQ is generated with respect to K. The timing for

the echo clocks is shown in Switching Characteristics on page 23.

Output Clock CQ Referenced with Respect to C. This is a free running clock and is synchronized to the input clock

for output data (C) of the DDR-II. In single clock mode, CQ is generated with respect to K. The timing for

the echo clocks is shown in Switching Characteristics on page 23.

Input

Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus

impedance. CQ, CQ, and Q output impedance are set to 0.2 x RQ, where RQ is a resistor connected

[x:0]

between ZQ and ground. Alternatively, this pin can be connected directly to V

, which enables the

DDQ

minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.

DOFF

Input

DLL Turn Off − Active LOW. Connecting this pin to ground turns off the DLL inside the device. The timing

in the DLL turned off operation is different from that listed in this data sheet. For normal operation, this

pin can be connected to a pull up through a 10 KΩ or less pull up resistor. The device behaves in DDR-I

mode when the DLL is turned off. In this mode, the device can be operated at a frequency of up to 167

MHz with DDR-I timing.

TDO

Output

Input

N/A

TDO for JTAG.

TCK

TCK Pin for JTAG.

TDI

TDI Pin for JTAG.

TMS

TMS Pin for JTAG.

Not Connected to the Die. Can be tied to any voltage level.

Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC

NC/36M

NC/72M

NC/144M

NC/288M

N/A

Input-

REF

Reference measurement points.

Power Supply Power Supply Inputs to the Core of the Device.

Ground

Ground for the Device.

Power Supply Power Supply Inputs for the Outputs of the Device.

DDQ

Document Number: 001-07160 Rev. *E

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CY7C1316CV18, CY7C1916CV18

CY7C1318CV18, CY7C1320CV18

mation presented to D

is also stored into the write data

are both asserted active. The 36 bits

Functional Overview

[17:0]

[1:0]

of data are then written into the memory array at the specified

location. Write accesses can be initiated on every rising edge of

the positive input clock (K). This pipelines the data flow such that

18 bits of data can be transferred into the device on every rising

edge of the input clocks (K and K).

The CY7C1316CV18, CY7C1916CV18, CY7C1318CV18, and

CY7C1320CV18 are synchronous pipelined Burst SRAMs

equipped with a DDR interface, which operates with a read

latency of one and half cycles when DOFF pin is tied HIGH.

When DOFF pin is set LOW or connected to V the device

behaves in DDR-I mode with a read latency of one clock cycle.

When Write access is deselected, the device ignores all inputs

after the pending write operations are completed.

Accesses are initiated on the rising edge of the positive input

clock (K). All synchronous input timing is referenced from the

rising edge of the input clocks (K and K) and all output timing is

referenced to the rising edge of the output clocks (C/C, or K/K

when in single clock mode).

Byte Write Operations

Byte write operations are supported by the CY7C1318CV18. A

write operation is initiated as described in the Write Operations

section. The bytes that are written are determined by BWS and

All synchronous data inputs (D

) pass through input registers

[x:0]

BWS , which are sampled with each set of 18-bit data words.

controlled by the rising edge of the input clocks (K and K). All

synchronous data outputs (Q ) pass through output registers

Asserting the appropriate Byte Write Select input during the data

portion of a write latches the data being presented and writes it

into the device. Deasserting the Byte Write Select input during

the data portion of a write enables the data stored in the device

for that byte to remain unaltered. This feature can be used to

simplify read/modify/write operations to a byte write operation.

[x:0]

controlled by the rising edge of the output clocks (C/C, or K/K

when in single-clock mode).

All synchronous control (R/W, LD, BWS

input registers controlled by the rising edge of the input clock (K).

) inputs pass through

[0:X]

CY7C1318CV18 is described in the following sections. The

same basic descriptions apply to CY7C1316CV18,

CY7C1916CV18, and CY7C1320CV18.

Single Clock Mode

The CY7C1318CV18 can be used with a single clock that

controls both the input and output registers. In this mode the

device recognizes only a single pair of input clocks (K and K) that

control both the input and output registers. This operation is

identical to the operation if the device had zero skew between

the K/K and C/C clocks. All timing parameters remain the same

in this mode. To use this mode of operation, tie C and C HIGH at

power on. This function is a strap option and not alterable during

device operation.

Read Operations

The CY7C1318CV18 is organized internally as two arrays of

512K x 18. Accesses are completed in a burst of two sequential

18-bit data words. Read operations are initiated by asserting

R/W HIGH and LD LOW at the rising edge of the positive input

clock (K). The address presented to address inputs is stored in

the read address register and the least significant bit of the

address is presented to the burst counter. The burst counter

increments the address in a linear fashion. Following the next K

clock rise, the corresponding 18-bit word of data from this

DDR Operation

The CY7C1318CV18 enables high-performance operation

through high clock frequencies (achieved through pipelining) and

double data rate mode of operation. The CY7C1318CV18

requires a single No Operation (NOP) cycle when transitioning

from a read to a write cycle. At higher frequencies, some appli-

cations may require a second NOP cycle to avoid contention.

address location is driven onto Q

, using C as the output

[17:0]

timing reference. On the subsequent rising edge of C the next

18-bit data word from the address location generated by the

burst counter is driven onto Q

. The requested data is valid

[17:0]

0.45 ns from the rising edge of the output clock (C or C, or K and

K when in single clock mode, 200 MHz and 250 MHz device). To

maintain the internal logic, each read access must be allowed to

complete. Read accesses can be initiated on every rising edge

of the positive input clock (K).

If a read occurs after a write cycle, address and data for the write

are stored in registers. The write information must be stored

because the SRAM cannot perform the last word write to the

array without conflicting with the read. The data stays in this

after the read(s), the stored data from the earlier write is written

into the SRAM array. This is called a posted write.

The CY7C1318CV18 first completes the pending read transac-

tions, when read access is deselected. Synchronous internal

circuitry automatically tri-states the output following the next

rising edge of the positive output clock (C). This enables a

seamless transition between devices without the insertion of wait

states in a depth expanded memory.

If a read is performed on the same address on which a write is

performed in the previous cycle, the SRAM reads out the most

current data. The SRAM does this by bypassing the memory

array and reading the data from the registers.

Write Operations

Write operations are initiated by asserting R/W LOW and LD

LOW at the rising edge of the positive input clock (K). The

address presented to address inputs is stored in the write

address register and the least significant bit of the address is

presented to the burst counter. The burst counter increments the

address in a linear fashion. On the following K clock rise the data

Depth Expansion

Depth expansion requires replicating the LD control signal for

each bank. All other control signals can be common between

banks as appropriate.

Programmable Impedance

presented to D

is latched and stored into the 18-bit write

[17:0]

data register, provided BWS

subsequent rising edge of the negative input clock (K) the infor-

are both asserted active. On the

An external resistor, RQ, must be connected between the ZQ pin

[1:0]

on the SRAM and V to enable the SRAM to adjust its output

Document Number: 001-07160 Rev. *E

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